Data input circuits and methods of inputing data for a synchronous semiconductor memory device

摘要

A data input circuit for a synchronous semiconductor memory device may comprise a detection unit for detecting whether the phase of a data strobe signal may lead or lag that of a clock signal. A delay unit may delay the data strobe signal by a first duration when the phase of the data strobe signal leads that of the clock signal and may delay the data strobe signal by a second duration when the phase of the data strobe signal lags that of the clock signal. A data input unit may synchronize a first input data signal previously fetched by the data strobe signal to the clock signal in response to an output signal of the delay unit. The data input circuit may effectively synchronize an input data signal using an internal delay that may be adjusted when a frequency of the clock signal may exceed a predetermined threshold.