GATE TECHNOLOGY FOR STRAINED SURFACE CHANNEL AND STRAINED BURIED CHANNEL MOSFET DEVICES

摘要

A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si_1-xGe_x layer on a substrate, a strained channel layer on the relaxed Si_1-xGe_x layer, and a Si_1-yGe_y layer; removing the Si_1-yGe_y layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.