Digital clock detection

摘要

A digital clock detector for detecting whether a digital clock, for providing an output alternating between a high value and a low value, is running or stopped, comprises: two or more digital delay gates connected to said clock, said delay gates being connected in a chain; and logic circuitry arranged to determine whether the logic levels on either side of each of said gates are the same or different, and to thereby provide an output which indicates whether said digital clock is running, or whether said digital clock has stopped while providing an output which corresponds to either said high value or said low value. <IMAGE>