发明名称 Electronics for a shock hardened data recorder
摘要 Electronics for a shock-hardened device, in particular a data recorder, incorporating non-volatile memory. The device has the functional elements: a signal conditioning circuit, an oscillator, an analog-to-digital converter (ADC), a field programmable gate array (FPGA), a trigger, and a non-volatile memory incorporating both electrically erasable programmable read only memory (EEPROM) and fast static random access memory (SRAM). As a recorder, the electronics enable efficient and reliable data recording in extreme shock environments, e.g., those involving dynamic testing of weapons such as target penetrating bombs or dual-stage warheads. It also provides for data retention upon loss or shutdown of power to the unit and yields high mean time between failures (MTBF) figures in more benign environments.
申请公布号 US6560494(B1) 申请公布日期 2003.05.06
申请号 US20000585730 申请日期 2000.06.02
申请人 THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY 发明人 SOTO GABRIEL H.;HADDON MICHAEL D.
分类号 G05B19/00;G05B23/02;(IPC1-7):G05B21/02 主分类号 G05B19/00
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