| 摘要 |
An integrated semiconductor memory device that can be subjected to a memory cell test in order to determine functional and defective memory cells includes addressable normal memory cells, a first redundancy unit having first addressable redundant memory cells and optically programmable switches for replacing an address of a defective normal memory cell by the address of a first redundant memory cell, and a second redundancy unit having second addressable redundant memory cells and electrically programmable switches for replacing an address of a defective normal memory cell by the address of a second redundant memory cell. The second redundancy unit can be connected by the activation of an irreversibly programmable switch, which enables a simplified functional test at the wafer level.
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