| 摘要 |
An apparatus, system and method for accelerating exchange (XCHG) instructions in a processor using a register alias table (RAT) data array and a content addressable memory (CAM) to handle register renaming. The RAT has at least one read port, at least one write port, and a plurality of address entries. The CAM has at least one read address, at least one write address, and a plurality of swap addresses. A plurality of logical register numbers are used as CAM input addresses to the RAT, and the operation of the CAM is completed in a first phase and a second phase of a clock cycle. The logical register numbers that match a pair of input swap addresses are interchanged.
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