发明名称 Semiconductor memory device having auxiliary conduction region of reduced area
摘要 A semiconductor memory device includes a semiconductor substrate; a plurality of word lines provided on the semiconductor substrate and arranged in parallel to each other; a plurality of memory cells provided along each of the plurality of word lines; a plurality of sub bit lines provided on the semiconductor substrate and arranged in parallel to each other, each of the plurality of word line intersecting the plurality of sub bit lines; a plurality of main bit lines arranged in parallel to the plurality of sub bit lines; a plurality of bank select lines arranged in parallel to the plurality of word lines; a plurality of bank select transistors provided along each of the plurality of bank select lines and connected to the respective sub bit lines; and a plurality of auxiliary conduction regions provided for each of the plurality of the main bit lines, connecting each of the plurality of the main bit lines to a set of the plurality of bank select transistors of the plurality of sub bit lines. The shape of the plurality of bank select transistors is the same. Each of the plurality of auxiliary conduction regions has a modified-H shape including a central portion connected to each of the plurality of main bit lines and branch portions each connected to a corresponding one of the set of the plurality of bank select transistors of the plurality of sub bit lines.
申请公布号 US6559514(B2) 申请公布日期 2003.05.06
申请号 US20000548888 申请日期 2000.04.13
申请人 SHARP KABUSHIKI KAISHA 发明人 MORIKAWA YOSHINAO
分类号 G11C17/08;H01L21/8246;H01L27/112;(IPC1-7):H01L29/06;G11C5/02;G11C5/06;G11C11/413 主分类号 G11C17/08
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