| 摘要 |
The present invention, in various embodiments, provides techniques for reducing effects of electrical impedance. In one embodiment, the impedance is in the form of inductance and arises from vias in a termination PCB and from resistors used on the PCB. In one embodiment, a power plane is placed near the resistors. Additional power and ground planes are created in parallel among themselves and perpendicular to the vias, which cause capacitance to be formed between each pair of the ground and power planes, the ground planes and the vias, and the power planes and the vias. In one aspect, the power plane near the resistors and the formed capacitance allow the high-frequency returned currents to flow through a smaller loop and thus be affected by a smaller inductance. Additionally, the created capacitance reduces both the total impedance of the vias and the resistors and any impedance that result from power-ground discontinuity.
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