发明名称 Fault propagation path estimating method, fault propagation path estimating apparatus and recording media
摘要 A gate connected to an input side of a normal signal line estimated-as in a logical state equal to an expected value with an implication operation is detected as a newly implication-capable gate, and a signal line on an output side of a gate estimated as in a logical state equal to the expected value with an implication operation for the implication-capable gate is initialized to a logical state before the implication operation. A signal line in which a logical contradiction occurs in the logical state estimated with the implication operation is registered, and the number of occurrences thereof is recorded. Additionally, the result of the implication operation is stored as history information, and when the number of occurrences of logical contradictions exceeds an allowable number, the history information is traced to initialize a logical state of a signal line causing the logical contradiction to a state before the implication operation until the number falls within the allowable number.
申请公布号 US6560738(B1) 申请公布日期 2003.05.06
申请号 US20000605737 申请日期 2000.06.29
申请人 NEC ELECTRONICS CORPORATION 发明人 SHIGETA KAZUKI
分类号 G01R31/28;G01R31/317;G01R31/3183;G06F17/50;(IPC1-7):G06F11/00;H04B17/00 主分类号 G01R31/28
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