In one embodiment, a programmable processor is configured to support a loop setup instruction. The loop setup instruction may be decoded and a zero offset loop may be detected from the loop setup instruction. The next instruction in the instruction stream may then be immediately issued as a first instruction in a loop. The loop setup instruction may also be used to detect a single instruction loop.
申请公布号
WO0242905(A3)
申请公布日期
2003.05.01
申请号
WO2001US46337
申请日期
2001.10.31
申请人
INTEL CORPORATION;ANALOG DEVICES, INC.
发明人
SINGH, RAVI, P.;ROTH, CHARLES, P.;OVERKAMP, GREGORY, A.