发明名称 Method for checking integrated circuits
摘要 A method for checking electrical networks, in which the geometric characteristics of all the components in the network are checked. Components that have predetermined geometric characteristics are marked. A test is then carried out to determine whether the marked components are disposed at required points in the network, that is to say whether they are interconnected as required. Conversely, it is also possible to check the interconnection of the components in the network, to mark the components with the required interconnection, and then to check whether they also have the required geometric characteristics.
申请公布号 US2003080767(A1) 申请公布日期 2003.05.01
申请号 US20020284779 申请日期 2002.10.31
申请人 NEUNHOFFER TILMANN;BAADER PETER;THOMAS CLAUDIA;NIELSEN ALEXANDER 发明人 NEUNHOFFER TILMANN;BAADER PETER;THOMAS CLAUDIA;NIELSEN ALEXANDER
分类号 G06F17/50;(IPC1-7):G01R31/02 主分类号 G06F17/50
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