发明名称 |
SRAM HAVING CELL INCLUDING STORAGE CAPACITOR AND METHOD FOR INPUTTING WRITE DATA THEREOF |
摘要 |
PURPOSE: An SRAM having a cell including a storage capacitor and a method for inputting write data thereof are provided to perform stably a write operation and a refresh operation by improving a structure of a circuit for performing the refresh operation and the write operation. CONSTITUTION: A refresh circuit(100) is used for driving a refresh operation according to a driving operation of a refresh timer. A write enable buffer(113) is used for storing a write enable signal. A delay signal driving portion(110) receives a refresh signal of the refresh circuit(100) and an output signal of the write enable buffer(113) and drives a delay signal. A write latch control portion(111) outputs a write latch control signal in response to a delayed clock of the write enable buffer(113). An address buffer(106) is synchronized with a clock edge of an internal clock signal in order to buffer selectively an external address or an internal address of a refresh counter(105).
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申请公布号 |
KR20030033508(A) |
申请公布日期 |
2003.05.01 |
申请号 |
KR20010065512 |
申请日期 |
2001.10.23 |
申请人 |
COREMAGIC INC. |
发明人 |
KIM, TAE HUN |
分类号 |
G11C11/413;(IPC1-7):G11C11/413 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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