发明名称 Method for generating logic simulation model
摘要 For each predetermined operational unit of a semiconductor device for which a logic simulation model is to be generated, several types of operational descriptions (MRS operating sections, bank selecting operating sections, and the like) having different functions are stored in advance as a group of operational description libraries in a hard disk. Then, specifying information which specifies operational descriptions that will be applied to the logic simulation model are inputted. The specified operational descriptions are then read out of the hard disk. Then a model body section which is the core of the logic simulation model is generated based on the read operational description. Thus, a method, an apparatus and a program for generating a logic simulation model, and a recording medium for recording the program, which can greatly reduce the procedures required for generating and maintaining the logic simulation model, are provided.
申请公布号 US2003083855(A1) 申请公布日期 2003.05.01
申请号 US20020131249 申请日期 2002.04.25
申请人 FUKUYAMA HIROYUKI 发明人 FUKUYAMA HIROYUKI
分类号 G06F17/50;G06F19/00;(IPC1-7):G06F17/50 主分类号 G06F17/50
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