| 摘要 |
The invention relates to an arrangement for realizing a binary counter which decrements or increments a partly permuted data word which is stored in a non-volatile memory (1), which arrangement is provided with a counter and a working memory (2), a data word being stored in the form of at least two memory words in the non-volatile memory (1), which arrangement: reads the memory words of the data word from the non-volatile memory (1) and stores these memory words in the working memory (2) while performing an inverse reordering of k permutation bits of the data word, applies an inverse bijective mapping function (permutation) to the k permutation bits of the data word, decrements or increments the data word, applies a bijective mapping function (permutation) to the k permutation bits of the data word, performs a reordering of the k permutation bits, and checks for each memory word whether it deviates from the memory word stored in the non-volatile memory (1) and stores only those memory words in the non-volatile memory (2) again for which this is the case, in order to increment a data word stored in the non-volatile memory (1), the bijective mapping function (permutation) being such that the k least significant bits of the data word, representing the k permutation bits whereto the mapping function is applied, change as infrequently as possible and approximately equally frequently due to the decrementing or incrementing after application of the mapping function, the reordering being performed in such a manner that the k permutation bits of the data word in the working memory are distributed among k memory words in the volatile memory.
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