| 摘要 |
A system (100) that may have a reduced power consumption during a standby state has been disclosed. A system (100) may include microprocessor unit (MPU) (101), a synchronous dynamic random access memory (SDRAM) controller (102), and a SDRAM (108). SDRAM controller (102) may include a power supply register (103) and a power supply control circuit (109). Power supply control register (103) may store an indicator as to whether or not data stored in SDRAM (102) is necessary. Power supply control circuit (109) may maintain or turn off a power supply to SDRAM (103) when system (100) enters a standby state in accordance with a value stored in power supply control register (103). In this way, current consumption in a standby state may be reduced and a time delay when a system (100) returns to a normal state may be reduced.
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