发明名称 Differential CMOS logic with dynamic bias
摘要 A CMOS circuit arrangement. In this arrangement, relatively thick oxide devices are fabricated along with relatively thin oxide devices on the same chip. High speed logic circuits are fabricated with thin oxide devices as differential logic operating with a low voltage swing. A current source is fabricated using thick oxide devices to drop a large percentage of the supply voltage, protecting the thin oxide devices from damage caused by large voltage swings. An adaptive bias control circuit receives inputs from the logic circuit or elsewhere to control the bias current available from the current source to permit larger currents to pass through the current source at switching times.
申请公布号 US2003080779(A1) 申请公布日期 2003.05.01
申请号 US20010002813 申请日期 2001.11.01
申请人 KNEE DEREK 发明人 KNEE DEREK
分类号 H03K19/094;(IPC1-7):H03K19/094 主分类号 H03K19/094
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