| 摘要 |
In a semiconductor memory device including a DLL circuit, a control logic includes a mode register, a command decoder, and a control signal generating unit outputting an output control signal of the DLL circuit. The control signal generating unit selects one of an ACT command and a READ command as a trigger for starting output of a clock, in accordance with a /CAS latency. When the /CAS latency is larger than a certain value, the READ command is used as the trigger. Output of the DLL clock can be stopped for a period from the input of the ACT command until the input of the READ command, so that power consumption can be reduced.
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