发明名称 Semiconductor memory device
摘要 The technique of the present invention sets a time period of a level H between a rise and a fall of an ATD signal (that is, a pulse width of the ATD signal) to be not shorter than a preset allowable address skew range and not longer than a time period between a timing of a rise of the ATD signal, at which the refreshing operation starts, and conclusion of the refreshing operation. This arrangement ensures generation of an appropriate ATD signal even when an address skew occurs in an externally given address.
申请公布号 US2003081487(A1) 申请公布日期 2003.05.01
申请号 US20020268782 申请日期 2002.10.11
申请人 SEIKO EPSON CORPORATION 发明人 MIZUGAKI KOICHI
分类号 G11C11/403;G11C7/22;G11C8/18;G11C11/406;G11C11/4076;(IPC1-7):G11C7/00 主分类号 G11C11/403
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