SYNCHRONIZE PROCESSING CIRCUIT

摘要

A synchronize processing circuit offers a stable supply of synchronizing signal to control circuits in display devices. A synchronize processing circ uit for multiscan display devices which display one type of video signals of multipl e video sources having different scanning frequencies comprises a PLL circuit for synchronizing regeneration of the synchronizing signal in the input video si gnalhaving a specified scanning frequency to output a re generation clock; a controller for generating a control signal; a first pulse generator which receives a synchr onizing signal in the video signal or the divided output signal of a divider built i n the PLL circuit, control signal, and regeneration clock, and outputs a synchronizing signal with a specified phase and width; an AFC circuit for outputting a synchroniz ing signal; a deflection output circuit which receives the synchronizing signal output from the AFC circuit and feeds back a synchronizing signal with the same phase as a deflection current frequency to the AFC circuit; and a second pulse generato r which receives the synchronizing signal output from the deflection output circuit and control signal, and outputs a synchronizing signal with a specified phase and width.