发明名称 Method and apparatus for evaluating a circuit
摘要 An apparatus and method for performance counter verification of an electronic circuit. The apparatus and method sends a transaction to a circuit under test causing counter values to change and retrieves these counter values from the circuit under test for comparison with known or expected counter values to measure the performance of the electronic circuit under test. The apparatus and method may also generate the known or expected counter values by monitoring the transactions sent to the circuit under test. The apparatus and method may also measure elapsed time for comparison with counter values retrieved from the circuit under test. The counter values can reflect a wide variety of events, including the occurrence of certain predefined events or the amount of time that elapses between two events.
申请公布号 US6557147(B1) 申请公布日期 2003.04.29
申请号 US20000562309 申请日期 2000.05.01
申请人 HEWLETT-PACKARD COMPANY 发明人 LEE MYEONG S.;SHARMA DEBENDRA DAS;BOCK JON
分类号 G01R31/319;G06F17/50;(IPC1-7):G06F17/50 主分类号 G01R31/319
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