| 摘要 |
A microcontroller enters a power saving mode in order to reduce power consumption. A logic circuit detects a power-saving mode release status irrespective of the occurrence of a power-saving mode release error due to incorrecct bit settings of control registers. Accordingly, the microcontroller recovers its normal operation. In a preferred embodiment, the microcontroller includes a clock generator that provides a microcontroller system clock signal, the microcontroller having a power-saving mode during activation of which the clock generator ceases generation of the microcontroller system clock signal. A power-save release detection circuit detects a transition in the level of at least one input/output data signal during operation in the power saving mode. In response to the transition, the power-save release detection circuit generates a power-save mode release signal to release the clock generator from the power saving mode, which causes the clock generator to resume generation of the microcontroller system clock signal.
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