| 发明名称 |
Method and apparatus for testing multi-port memories |
| 摘要 |
A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.
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| 申请公布号 |
US6557127(B1) |
申请公布日期 |
2003.04.29 |
| 申请号 |
US20000514870 |
申请日期 |
2000.02.28 |
| 申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
ADAMS R. DEAN;ECKENRODE THOMAS J.;GREGOR STEVEN L.;ZARRINEH KAMRAN |
| 分类号 |
G01R31/28;G01R31/3183;G06F12/16;G11C29/52;G11C29/56;(IPC1-7):G11C29/00 |
主分类号 |
G01R31/28 |
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