| 摘要 |
PURPOSE: A circuit of decoding an MPEG-4 RVLC(Reversible Variable Length Code) is provided to divide an RVLC into 3 clusters to divide the code, and to use a pattern matcher for detecting the clusters, thereby supplying a small-sized decoder at a high speed. CONSTITUTION: An input buffer end(IB) arranges and outputs certain bits. The second pattern matcher(CD2) determines the first cluster with upper 2 bits or 3 bits, inputs bit strings except the number of bits of the first cluster, and outputs the second cluster. The third pattern matcher(CD3) makes the rest output bits of the second pattern matcher as input data, and obtains a consecutive 1. A length operator(LEN_CAL) adds output information of the second and the third pattern matcher, and calculates length of codeword. Two look-up tables(LUT1,LUT2) store symbols of the codeword in a forward and a reverse table. A fixed length decoder(FLD) decodes fixed length codes that do not exist in the look-up tables. A result selector(OSEL) generates an index of a codeword table by using cluster information. |
