发明名称 SUPER SCALAR PROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide a super scalar processor using tags for controlling the execution of an instruction. SOLUTION: This super scalar unit 104 comprises a resistor file 202, tags FIFO 204, and a control logic 207. Information necessary for the execution of each instruction by an instruction window is fed from an instruction source 102 to the resistor file 202 through a bus 103. A queue comprises a plurality of slots 206 containing the tags, and the tags are attached to the instruction. The tags are arranged in the queue in an order specified by the program order of their corresponding instructions. The control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction.
申请公布号 JP2003122564(A) 申请公布日期 2003.04.25
申请号 JP20020246586 申请日期 2002.08.27
申请人 SEIKO EPSON CORP 发明人 IADONATO KEVIN R;DEOSARAN TREVOR A;GARG SANJIV
分类号 G06F9/30;G06F9/34;G06F9/38;(IPC1-7):G06F9/38 主分类号 G06F9/30
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