| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the number of pins of an LSI and the number of components of a peripheral circuit by performing DV decoding process with single clock. SOLUTION: This digital signal processor uses a clock signal generating means for generating a clock signal asynchronous with an input signal, a frequency demultiplying means for demultiplying the frequency of the clock signal outputted from the clock signal generating means and outputting a prescribed clock enabling signal, a digital interface processing means for isolating and outputting a compressed image, aural information, etc., from a compression- processed digital signal, in accordance with the enabling signal outputted from the frequency demultiplying means, a video signal processing means for decoding compressed image information outputted from the digital interface processing means, obtaining an image signal and at the same time, synchronizing the image signal with the input signal, and an audio signal processing means for decoding the aural information outputted from the digital interface processing means, obtaining an aural signal, and at the same time, outputting the aural signal synchronously with an aural operation mode.</p> |
