DIGITAL SIGNAL PROCESSOR, PROGRAM CONVERTER AND COMMUNICATION SYSTEM HAVING DIGITAL SIGNAL PROCESSOR

摘要

PROBLEM TO BE SOLVED: To provide a digital signal processing circuit such as a digital signal processor capable of reducing the power consumption by controlling the supply or stop of a clock signal to a data memory even in any access form of continuous access or random access without generating any adverse influence such as the decrease of the operating frequency or the increase of the number of pipe line stages. SOLUTION: This digital signal processor is provided with a bank group decoder 4 for specifying a bank or bank group indicated by an address held in each of address pointer registers P0-P3 and a bank group register 5 in which the decode result of the bank group decoder 4 is held. And, the supply and stop of a clock signal to the bank group of a data memory 3 is controlled according to the value of each bank group register 5.