发明名称 VIDEO SIGNAL DECODER DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a digital video signal decoder device to generate a clock of the suitable frequency for Y/C separation, synchronism separation, and demodulation processing from a clock obtained from an oscillator of the suitable frequency for the MPEG for process. SOLUTION: This device comprises an oscillation means such as a quartz oscillator generating a first clock; clock generation means 11, 12 and 16 which form sine wave data of the time line generated based on a first clock, and generate a second clock even number twice subcarrer; a Y/C separation/ demodulation means 14 for performing Y/C separation processing, synchronism separation and demodulation processing by using the second clock; a signal rate conversion means 13 that converts a signal outputted from the Y/C separation/demodulation means 14 to the first clock; and a signal processing means 16 that generates a Y/Cr/Cb signal by using the first clock.
申请公布号 JP2003125421(A) 申请公布日期 2003.04.25
申请号 JP20010321319 申请日期 2001.10.19
申请人 HITACHI LTD 发明人 NONAKA SHINICHI
分类号 H04N9/804;H04N9/44;H04N9/808;(IPC1-7):H04N9/44 主分类号 H04N9/804
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