发明名称 METHOD FOR REDUCING SLEW RATE ON TRANSITION EDGE OF DIGITAL SIGNAL ON INTEGRATED CIRCUIT NODE
摘要 PROBLEM TO BE SOLVED: To reduce a slew rate on the transition edges of a digital signal on a node of an integrated circuit. SOLUTION: A number of switchably conductive devices such as FETs each characterized by a different threshold voltage are connected in parallel between a transmission line node such as an output pad and a voltage source. Each conductive device is controllable at a respective switch using a common driving signal. Accordingly, when the driving signal transitions from one digital state to another, the conductive devices will each turn on or off (depending on the direction of the signal transition) in turn to generate a stepped control of the slew rate of the signal edge on the node.
申请公布号 JP2003124799(A) 申请公布日期 2003.04.25
申请号 JP20020215291 申请日期 2002.07.24
申请人 AGILENT TECHNOL INC 发明人 HUMPHREY GUY HARLAN
分类号 H03K5/12;H03K17/16;H03K17/687;H03K19/0175;(IPC1-7):H03K19/017 主分类号 H03K5/12
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