发明名称 |
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY |
摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the increment of chip area is small and which is provided with a high speed input initial stage latch. SOLUTION: A semiconductor device comprises: a first latch for receiving an input signal and holding the input signal for only a half cycle period of a first clock signal; a delay element connected to the output of the first latch; a second latch connected to the output of the delay element and holding a signal supplied from the delay element for only a half cycle period of a second clock signal; and a circuit for adjusting at least one of the timings of the first clock signal and the second clock signal so that a signal latched with the first latch in the half cycle of the first clock signal is latched by the second latch through the delay element in the half cycle period of a succeeding second clock signal.</p> |
申请公布号 |
JP2003123478(A) |
申请公布日期 |
2003.04.25 |
申请号 |
JP20010307901 |
申请日期 |
2001.10.03 |
申请人 |
FUJITSU LTD |
发明人 |
KAWABATA KUNINORI |
分类号 |
G11C11/413;G06F1/10;G06F1/12;G11C7/00;G11C7/10;G11C11/407;G11C11/408;H03K3/037;(IPC1-7):G11C11/413 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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