| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory with a reduced area of a memory cell array while maintaining the same function as that of a conventional one. SOLUTION: The memory cell array of the non-volatile semiconductor memory comprises a plurality of gate electrodes arranged in rows, bit lines D1, D2, D3, and D4 and source lines S1, S2, S3, and S4 which are arranged in columns, and memory cells having a floating gate. The source lines are disposed separately in two or more interconnection layers, with the source line S2 disposed in the first layer overlapping the source line S1 disposed in the second layer in top view. Due to this array structure, the dimension in the row direction of the memory cell array can be reduced, remarkably reducing the area thereof.</p> |
