发明名称 Method for creating an intergrated circuit stage wherein fine and large patterns coexist
摘要 Successive use is made of a layer of radiation-sensitive resin at points (4') intended to form the wide semi-conductor patterns in a still intact layer (2), under at least one hard mask (3'), then of a resin sensitive to particle bombardment (6) over fine patterns to be formed in this same layer (2), which may be juxtaposed to those previously mentioned. The first resin patterns are exposed collectively and rapidly by insolation, while electron bombardment allows fine patterns to be formed with great precision. Another hard mask (9) was deposited before the second resin (6) and forms flanks (10) around the wide patterns, which protect the latter from lateral attacks during etching.
申请公布号 US2003077899(A1) 申请公布日期 2003.04.24
申请号 US20020296197 申请日期 2002.11.29
申请人 DELEONIBUS SIMON 发明人 DELEONIBUS SIMON
分类号 G03F7/26;H01L21/027;H01L21/3065;H01L21/8234;(IPC1-7):H01L21/44;H01L21/320 主分类号 G03F7/26
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