发明名称 |
Method for generating transition delay fault test patterns |
摘要 |
A method of generating transition delay fault test patterns creates first and second circuit models of a received circuit model. The second circuit model is a replication of the first circuit model. Each latch of the first circuit model is identified. On a sequential basis until the entire circuit model is transformed, the data input of an identified latch in the first circuit model is disconnected and the data output of the corresponding latch in the second circuit model is disconnected. The driver of the data input of the latch in the first circuit model is connected to what was driven by the data output of the corresponding latch in the second circuit model to form a transformed circuit model. Stuck-at fault testing using conventional ATPG tools is performed on the transformed circuit model and the resulting test vectors are translated to generate transition fault test patterns for the original received circuit model.
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申请公布号 |
US2003079189(A1) |
申请公布日期 |
2003.04.24 |
申请号 |
US20010986211 |
申请日期 |
2001.10.22 |
申请人 |
ABADIR MAGDY S.;ZHU JUHONG |
发明人 |
ABADIR MAGDY S.;ZHU JUHONG |
分类号 |
G01R31/3183;(IPC1-7):G06F17/50 |
主分类号 |
G01R31/3183 |
代理机构 |
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