Chipset with LPC interface and data accessing time adapting function

摘要

A chipset with LPC interface and data accessing time adapting function is proposed. The chipset comprises an LPC slave controller connected to an LPC master controller in a main controller, a LPC/ISA bridge connected to the LPC slave controller and convert a data in LPC specification to a data in ISA specification, a plurality of ISA logic control units connected to the LPC/ISA bridge and controlling corresponding ISA devices, and a data accessing time adjuster connected to the LPC/ISA bridge and adjusting the time of accessing operation for an ISA or LPC device.