发明名称 Internal command signal generator for memory e.g. DRAM, generates memory-internal command signal at time point dependent on memory-internal command signal
摘要 A command input (212) receives a memory operation command (SP-OP-BEFEHL) for performing a memory operation in a memory system (232). A clock signal input (216) receives an external clock signal (CLK). An output (228) provides a memory-internal command system (INT-BEFEHL) on a command signal wire of the memory system. A command signal generator (220) uses the memory operation command to generate the memory-internal command signal at a time point dependent on the command signal (INT-BEFEHL). The command signal generator is adjustable, optionally synchronous with a rising or falling edge of the external clock signal.
申请公布号 DE10149192(A1) 申请公布日期 2003.04.24
申请号 DE20011049192 申请日期 2001.10.05
申请人 INFINEON TECHNOLOGIES AG 发明人 KHO, REX;TAEUBER, ANDREAS;SCHMOELZ, PAUL
分类号 G11C7/10;G11C7/22;(IPC1-7):G11C7/22 主分类号 G11C7/10
代理机构 代理人
主权项
地址