Dynamic random access memory has read clock generator which is arranged in memory module, so that data bus and read clock bus are substantially symmetric

摘要

The data buses (116,118) connected to a controller (112), read data from the memory modules (100,102) and write the data into the modules. The read clock generators (124a,124b) generate a read clock with which the data are transferred from the module to the controller. The generators are arranged in the module, so that the data buses and the read clock buses (120,122) are substantially symmetric.