| 摘要 |
1. An apparatus for buffering and isolating a signal source from an external load, said apparatus having a signal input terminal for receiving an input signal from said signal source and a signal output terminal for providing an output signal, corresponding to said input signal to said external load, comprising: a first bias current source providing a first emitter current to a first driver transistor and a first bias current to a first output transistor; a second bias current source receiving a second emitter current from a second driver transistor and a second bias current from a second output transistor, said input signal biasing said first driver transistor and said second driver transistor, and said output terminal being electrically coupled to an emitter of said first output transistor and to an emitter of said second output transistor; and, characterized in that comprises a control voltage source for providing said control voltage source and being electrically coupled between an emitter of said first driver transistor and an emitter of said second drive transistor, wherein said first bias current and said second bias current vary as a predetermined function of said control voltage. 2. An apparatus according to claim 1, wherein said first driver transistor includes a PNP type transistor, said second driver transistor includes an NPN type transistor, said first output transistor includes an NPN type transistor, and said second output transistor includes a PNP type transistor. 3. An apparatus according to claim 1, further including supply voltage sources electrically coupled between a collector of said first output transistor and a collector of said second output transistor. 4. An apparatus according to claim 1, wherein said predetermined function includes a substantially exponential relationship. 5. An apparatus according to claim 1, wherein a quiescent current through said first output transistor and a quiescent current through said second output transistor are substantially independent of said first current source and said second current source. 6. An apparatus according to claim 1, wherein said control voltage source includes a resistor, a PNP type transistor, and an NPN type transistor, said resistor being electrically coupled between a collector of said PNP type transistor and a collector of said NPN type transistor, a base of said PNP type transistor being electrically coupled to said collector of said NPN type transistor, a base of said NPN transistor being electrically coupled to said collector of said PNP type transistor, an emitter of said PNP type transistor being electrically coupled to said emitter of said first driver transistor, and an emitter of said NPN type transistor being electrically coupled to said emitter of said second drive transistor. 7. An apparatus for buffering and isolating a signal source from an external load, said apparatus having a signal input terminal for receiving an input signal from said signal source and a signal output terminal for providing an output signal to said external load, comprising an output stage, including a first NPN type transistor having a first quiescent collector current, and a first PNP type transistor having a second quiescent collector current, an input stage including a second PNP type transistor and a first current source, a second NPN type transistor, a first current source and a second current source, wherein a first NPN type transistor emitter being electrically coupled to a first PNP type transistor emitter, a first NPN type transistor collector being coupled to a first voltage supply source, and a first PNP type transistor collector being coupled to a first voltage supply source and a first NPN type transistor collector being coupled to a second voltage supply source, a second PNP type transistor emitter being electrically coupled to a first current source output terminal and to said first NPN type transistor base, a second PNP type transistor collector being electrically coupled to said second voltage supply source, a second PNP type transistor base being electrically coupled to said signal input terminal, and a first current source input terminal being electrically coupled to said first voltage supply source, a second NPN type transistor emitter being electrically coupled to said second current source input terminal and to said first PNP type transistor base, a second NPN type transistor collector being electrically coupled to said first voltage supply source, a second NPN type transistor base being electrically coupled to said signal input terminal, and a second current source output terminal being electrically coupled to said second voltage supply source, and comprises a control voltage source for providing control voltage and having a positive terminal and a negative terminal, said positive terminal being electrically coupled to said first NPN type transistor base and said negative terminal being electrically coupled to said first PNP type transistor base, wherein said first quiescent collector current and said second quiescent collector current vary as a predetermined function of said control voltage. 8. An apparatus according to claim 7, wherein said predetermined function includes a substantially exponential relationship. 9. An apparatus according to claim 7, wherein said control voltage source includes a resistor, a third PNP type transistor, and a third NPN type transistor, said resistor being electrically coupled between a collector of said third PNP type transistor and a collector of said third NPN type transistor, a base of said third PNP type transistor being electrically coupled to said collector of said third NPN type transistor, a base of said third NPN transistor being electrically coupled to said collector of said third PNP type transistor, an emitter of said third PNP type transistor being electrically coupled to said emitter of said first driver transistor, and an emitter of said third NPN type transistor being electrically coupled to said emitter of said second drive transistor. 10. A buffer stage for buffering and isolating a signal source from an external load, said stage having a signal input terminal for receiving an input signal from said signal source and a signal output terminal for providing an output signal to said external load and corresponding to said input signal, the buffer stage comprising an input section including at least two driver transistors each arranged so as to operate with a predetermined bias current; an output section including at least two output transistors each arranged so as to operate with a predetermined quiescent current; and a voltage source being coupled to the input and output sections and constructed and arranged so as to set the quiescent currents flowing through the output transistors substantially independent of the size of the bias current flowing through the driver transistors. 11. A buffer stage according to claim 10, wherein adjusting the voltage provided by the voltage source causes the bias currents through the two driver transistors to be split at different ratios. 12. A buffer stage according to claim 10, wherein the quiescent current through the output transistors is substantially independent of the size of the emitter area of each of the driver transistors.
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