发明名称 |
High performance address decode technique for arrays |
摘要 |
An address decoder having pre-decode logic circuitry positioned in between ends of final decode logic circuitry is provided. Such an address decoder yields less wire load, less gate load, less power consumption, and increased speed due to the pre-decode logic circuitry having to be capable of only driving a signal over half the length of a final decoder. Further, a method to select memory elements from a memory array using centrally positioned pre-decode logic circuitry is provided.
|
申请公布号 |
US2003076732(A1) |
申请公布日期 |
2003.04.24 |
申请号 |
US20010003008 |
申请日期 |
2001.10.23 |
申请人 |
KANT SHREE;RAMACHANDRAN APARNA |
发明人 |
KANT SHREE;RAMACHANDRAN APARNA |
分类号 |
G11C8/10;(IPC1-7):G11C8/00 |
主分类号 |
G11C8/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|