| 摘要 |
Processor circuitry such as a "system-on-chp" (SOC) device comprises one or more processing units (40, 42), at least first and second debug event detectors (12, 14), each for detecting when a debug event occurs in one of the processing units, and a debug correlation element (16) comprising a counter (18) for holding a count value (20). Interconnection circuitry (22) provides a first signal path (24) between the first debug event detector and the debug correlation element and a second signal path (26) between said second debug event detector and the debug correlation element. each signal path serves to transmit at least one control signal to/from the debug correlation element so as to establish a debug relationship between the first and second debug event detectors. In such processor circuitry complex debug relationships can be estbalished between the debug event detectors involving filtering and counter functions. |
