发明名称 BURN-IN TESTING CIRCUIT OF SEMICONDUCTOR INTEGRATION CIRCUIT, AND METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To enhance the toggle ratio in the burn-in testing of a functional macros, and to suppress developing time of the burn-in test. SOLUTION: The burn-in test is performed using a memory BIST circuit 202, designed so as to preliminarily perform all tests necessary for confirming the operation of a memory device 201 for not only enhancing the toggle ratio in the burn-in test of the memory device, but also to suppress the developing time of the burn-in testing. Further, by performing the scanning design of the memory BIST circuit 202, the burn-in test of the memory BIST circuit 202 is performed efficiently, and the toggle ratio of the whole of the burn-in test can be enhanced.
申请公布号 JP2003121508(A) 申请公布日期 2003.04.23
申请号 JP20010314625 申请日期 2001.10.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HINOSUGI MASAKI
分类号 G01R31/26;G01R31/28;G01R31/30;G11C29/00;G11C29/06;G11C29/12;(IPC1-7):G01R31/30 主分类号 G01R31/26
代理机构 代理人
主权项
地址
您可能感兴趣的专利