| 摘要 |
PURPOSE: An apparatus for testing a plurality of semiconductor ICs in parallel is provided to reduce the burden on a hardware even when the number of semiconductor ICs subject to parallel test is increased. CONSTITUTION: The testing apparatus includes a test circuit(100) for devices subject to test (e.g., semiconductor ICs)(121,122,123,124), first switches(111,113,115,117) corresponding respectively to the subject devices and second switches(112,114,116,118) corresponding respectively to the subject devices. The first switches(111,113,115,117) supply a line voltage to the subject devices(121,122,123,124) in response to a selection signal provided from a control circuit in the test circuit(100). The second switches(112,114,116,118) supply common test data provided from a pattern memory(102) in the test circuit(100) to the input terminals of the subject devices in response to the selection signal.
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