发明名称 System and method for verifying configuration of a programmable logic device
摘要 A system and method utilize bitmaps for verifying configuration of a programmable logic device (PLD). A configuration bitstream containing configuration commands and data is converted to a configuration bitmap. The configuration bitstream is downloaded to PLD, thus programming the PLD. Readback commands and data read back from the PLD are used to generate a readback bitstream. The readback bitstream is then converted to a readback bitmap. Bits at corresponding cell locations in the readback bitmap and the configuration bitmap are compared. An error signal is output if the bits are different. In one embodiment, a mask bitmap is generated to indicate which cell locations are non-configuration memory cells and thus need not be compared.
申请公布号 US6553523(B1) 申请公布日期 2003.04.22
申请号 US19990374251 申请日期 1999.08.13
申请人 LINDHOLM JEFFREY V.;ALLAMSETTY CHAKRAVARTHY K. 发明人 LINDHOLM JEFFREY V.;ALLAMSETTY CHAKRAVARTHY K.
分类号 G01R31/3185;(IPC1-7):G01R31/28 主分类号 G01R31/3185
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