发明名称 |
Clocking scheme for ASIC |
摘要 |
A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronizers.
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申请公布号 |
US6552590(B2) |
申请公布日期 |
2003.04.22 |
申请号 |
US20010879065 |
申请日期 |
2001.06.13 |
申请人 |
3COM CORPORATION |
发明人 |
PRATT SUSAN M;GAVIN VINCENT;CREEDON TADHG;HUGHES SUZANNE M;LARDNER MIKE;O'REILLY PADRAIC |
分类号 |
G06F1/12;G06F5/06;(IPC1-7):H03K3/00 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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