Method for patterning a silicon-on-insulator photomask

摘要

A method for generating a patterned SOI photomask used for embedded DRAMs is described. The method systematically identifies embedded DRAM areas to be excluded from the SOI process and generates the shapes to be printed on the photomask so that the embedded DRAM may be fabricated on bulk silicon. The method includes the steps of: identifying and sorting DRAM array well shapes by common electrical net, resulting in a single array well shape for each electrical net (i.e., embedded DRAM cell). Next, all the n-band contacts touching a given array well shape are collected. These shapes are merged by common electrical net. A shape is then generated which is the smallest enclosing rectangle of the common electrical net of the n-band contact shapes. This represents the patterned SOI shape and defines the bulk areas onto which the embedded DRAM is to be built. Accordingly, the embedded DRAM macro is constructed in bulk areas while the logic is constructed in SOI.