发明名称 |
Method of reading and logically OR'ing or AND'ing a four-transistor memory cell array by rows or columns |
摘要 |
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically OR'ing or AND'ing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).
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申请公布号 |
US6552924(B1) |
申请公布日期 |
2003.04.22 |
申请号 |
US20020061876 |
申请日期 |
2002.01.31 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
BROOKS ROBERT J;NEUDECK ALEXANDER J |
分类号 |
G11C11/412;G11C11/418;(IPC1-7):G11C11/00 |
主分类号 |
G11C11/412 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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