发明名称 |
Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration |
摘要 |
A test signal generating circuit generates internal test control signals from a small number of signals supplied via an address terminal in a test mode operation. According to the test control signals, the values of internal row address signal bits from an address buffer are set, while a row-related control circuit with test control function controls operations of a row selection circuit and bit line peripheral circuitry according to the test control signals. A plurality of word lines are driven simultaneously into a selected state and an acceleration test is performed according to a small number of control signals in a short period of time. Voltage stress applied between memory cell capacitors and between word lines can be accelerated with a small number of control signals.
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申请公布号 |
US6551846(B1) |
申请公布日期 |
2003.04.22 |
申请号 |
US20000642751 |
申请日期 |
2000.08.18 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
FURUTANI KIYOHIRO;ASAKURA MIKIO;KATOH TETSUO |
分类号 |
G11C11/401;G11C29/06;G11C29/34;H01L23/544;(IPC1-7):G01R31/26;H01L21/66 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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