发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR MEMORY USING THIS CIRCUIT
摘要 PURPOSE: To increase the operation speed of a decoding circuit by making circuit constitution requiring no decoder control signal Π2 out of a control signal Π1 of an address buffer and a control signal Π2. CONSTITUTION: The above mentioned purpose is achieved by uniting an address buffer and a decoder and by providing such a constitution that an output current path of a decoding output is connected in series to a transistor constituting the address buffer and the decoder. When this decoding circuit is used for a semiconductor memory, the access time can be increased, power consumption can be reduced, and the number of cycles can be increased.
申请公布号 KR20030031435(A) 申请公布日期 2003.04.21
申请号 KR20020062399 申请日期 2002.10.14
申请人 HITACHI ULSI SYSTEMS CO., LTD.;KABUSHIKI KAISHA HITACHI SEISAKUSHO(D/B/A HITACHI, LTD.) 发明人 KANETANI KAZUO;NAMBU HIROAKI
分类号 G11C11/413;G11C8/10;G11C11/34;H03K19/096;(IPC1-7):G11C11/34 主分类号 G11C11/413
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