发明名称 CLOCK CROSSOVER CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a clock switching circuit in which work efficiency can be prevented from being lowered by keeping the continuity of data even when a clock to be applied is changed. SOLUTION: A clock difference measurement logic circuit 19 detects a difference between an estimated clock and an applied clock. On the basis of the detected result, a word deciding logic circuit 20 determines the read timing of a RAM 12 and stores it in a length buffer 17 so that the continuity of data disordered by the clock difference can be recovered. The data stored in the RAM 12 are read on the basis of the timing stored in the length buffer 17.</p>
申请公布号 JP2003115826(A) 申请公布日期 2003.04.18
申请号 JP20010307011 申请日期 2001.10.03
申请人 NEC CORP 发明人 FUKAGAWA MASAO
分类号 G06F13/38;G06F1/12;H04L7/00;(IPC1-7):H04L7/00 主分类号 G06F13/38
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