| 摘要 |
PURPOSE: A method for fabricating a semiconductor device with a T-shaped gate electrode is provided to reduce the parasitic capacitance of the transistor by decreasing the area of the source/drain overlapped with the gate electrode. CONSTITUTION: A gate insulating layer and a bottom gate layer are formed on a semiconductor substrate(200). The bottom gate layer is doped, and a top gate layer is formed on the entire surface of the doped bottom gate layer. The top and the bottom gate layers are sequentially patterned such that a gate insulating layer pattern(202n,202p) and a gate electrode(204n,204p,214) are sequentially formed on the semiconductor substrate(200), and both lateral walls of the gate electrode(204n,204p) have an undercut region(C). The semiconductor substrate(200) with the gate electrode(204n,204p,214) then suffers the thermal oxidation such that a thermally oxidized film(216) is formed on the exposed surface of the gate electrode(204n,204p,214).
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