发明名称 MULTIPLEXED DATA PROCESSING SYSTEM
摘要 PROBLEM TO BE SOLVED: To reduce a hardware quantity, to miniaturize a device and to reduce power consumption by easily generating a check timing for the channel unit of respective low speed data in a multiplexed data processing system for multiplexing the respective low speed data in a low-order group to high speed data. SOLUTION: Multiplexed main signal data are checked in a unit of a low speed channel in a data check part 9-1, and a number of times of alarm detection is counted for each channel by an alarm protecting part 9-2 and held in an alarm information storage part 9-8. A timing signal presenting the check range in the channel unit is generated by a timing generating and sending part 1-4 on the basis of multiple information, which is applied in the unit of a time slot by a software control signal, in the unit of the time slot by holding this multiple information through a serial/parallel converting part 1-1 into a time slot information setting part 1-2. The multiple information in the unit of the time slot is used for adding processing of additional information for check and setting of loop back control information or the like as well.
申请公布号 JP2003115809(A) 申请公布日期 2003.04.18
申请号 JP20010311781 申请日期 2001.10.09
申请人 FUJITSU LTD 发明人 YANO MASARU;HIRAYAMA RYOJI;KITANO KOICHI;ARAI TAKENORI
分类号 H04J3/00;H04Q11/04;(IPC1-7):H04J3/00 主分类号 H04J3/00
代理机构 代理人
主权项
地址