| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor architecture of a RISC-based high performance superscalar type in which architecture functions can be easily strengthened. SOLUTION: An instruction fetch unit 102 to fetch an instruction set, and an execution unit 104 having a function of executing plural instructions simultaneously through a parallel array of function units are provided. The instruction fetch unit 102 holds a prescribed number of instructions in an instruction buffer. The execution unit 104 is provided with an instruction selecting unit connected to the instruction buffer to select an instruction to be executed, and the plural function units to execute an operation designated by the instruction. The instruction selecting unit includes an instruction decoder to determine if the instruction to be executed is usable or not, related logic, and an instruction scheduler coupled with each of the function units to determine respective execution status to schedule start of processing of the instruction through the function units. |
